The two major types of digital filters are finite impulse response digital filters (FIR filters) and infinite impulse response digital filters (IIR). Both types have some advantages and disadvantages that should be carefully considered when designing a filter.
I 'm looking for the best RC time constant and its reason in a PWM to convert digital signal to analog based on duty-cycle and frequency and other parameters. PWM frequency is 10 kHz.
stevenvh5 Answers
$begingroup$The best RC is infinite, then you have a perfectly ripple-less DC output. Problem is that it also takes forever to respond to changes in the duty cycle. So it's always a tradeoff.
A first-order RC filter has a cutoff frequency of
$ f_c = dfrac{1}{2 pi RC} $
and a roll-off of 6 dB/octave = 20 dB/decade. The graph shows the frequency characteristic for a 0.1 Hz (blue), a 1 Hz (purple) and a 10 Hz (the other color) cutoff frequency.
So we can see that for the 0.1 Hz filter the 10 kHz fundamental of the PWM signal is suppressed by 100 dB, that's not bad; this will give very low ripple. But!
Justin timberlake like i love you instrumental download youtube. This graph shows the step response for the three cutoff frequencies. A change in duty cycle is a step in the DC level, and some shifts in the harmonics of the 10 kHz signal. The curve with the best 10 kHz suppression is the slowest to respond, the x-axis is seconds.
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This graph shows the response of a 30 µs RC time (cutoff frequency 5 kHz) for a 50 % duty cycle 10 kHz signal. There's an enormous ripple, but it responds to the change from 0 % duty cycle in 2 periods, or 200 µs.
This one is a 300 µs RC time (cutoff frequency 500 Hz). Still some ripple, but going from 0 % to 50 % duty cycle takes about 10 periods, or 1 ms.
Further increasing RC to milliseconds will decrease ripple further and increase reaction time. It all depends on how much ripple you can afford and how fast you want the filter to react to duty cycle changes.
This web page calculates that for R = 16 kΩ and C = 1 µF we have a cutoff frequency of 10 Hz, a settling time to 90 % of 37 ms for a peak-to-peak ripple of 8 mV at 5 V maximum.
edit
You can improve your filter by going to higher orders:
The blue curve was or simple RC filter with a 20 dB/decade roll-off. A second order filter (purple) has a 40 dB/decade roll-off, so for the same cutoff frequency will have 120 dB suppression at 10 kHz instead of 60 dB. These graphs are pretty ideal and can be best attained with active filters, like a Sallen-Key.
Equations
Peak-to-peak ripple voltage for a first order RC filter as a function of PWM frequency and RC time constant:
$ V_{ripple} = dfrac{ e^{dfrac{-d}{f_{PWM} RC}} cdot (e^{dfrac{1}{f_{PWM} RC}} - e^{dfrac{d}{f_{PWM} RC}}) cdot (1 - e^{dfrac{d}{f_{PWM} RC}}) }{1 - e^{dfrac{1}{f_{PWM} RC}}} cdot V_+$
E&OE. 'd' is the duty cycle, 0.1. Ripple is the largest for d = 0.5.
Step response to 99 % of end value is 5 x RC.
Cutoff frequency for the Sallen-Key filter: Iphoto for os x maverick.
$ f_c = dfrac{1}{2 pi sqrt{R1 text{ } R2 text{ } C1 text{ } C2}} $
For a Butterworth filter (maximum flat): R1 =R2, C1 = C2
stevenvhstevenvhAs Steven said, it's a tradeoff between attenuating the PWM frequency versus response time. This is why any such decision has to start with a spec of what you want from the resulting analog signal. What signal to noise ratio does it need to be, or at least how much noise at the PWM frequency can you tolerate? How fast does it have to settle to the noise floor level? Or conversely, what is the upper frequency you care about?
Note that it may not be possible to meet a particular set of criteria with a particular PWM output. Let's say you wanted good quality voice output. We'll say that's up to 8 kHz and 60 dB signal to noise. That isn't going to happen with any reasonably tractable analog filter with 20 kHz PWM, and certainly not with anything as simple as a single R and C.
As a example, let's work backwards and see what the PWM characterstics would have to be to support the above voice example with a single R,C filter. We've already said the -3 dB rolloff frequency is 8 kHz, so that's what we set the R and C to. The rolloff frequency of a single R,C filter is:
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F = 1 / (2 π R C)
When R is in Ohms, C in Farads, then F is in Hertz. It should be obvious this equation can be rearranged to solve for any of R, C, or F given the other two. I keep 1/(2 π) = .15915 always in a register in my calculator because this computation comes up regularly in electronics. Then I simply divide that by two of R, C, or F to get the third.
We have two degrees of freedom and the above equation only nails down one of them. The other can be thought of as the impedance you want the resulting signal to have. Let's shoot for around 10 kΩ, which is what we'll make R just to see what C comes out to:
1 / (2 π 8kHz 10kΩ) = 1.99 nF
That's basically the standard capacitor value of 2 nF, so we'll just go with that. If it hadn't come out to a common value, we'd have picked a near one then gone back and adjusted R accordingly. Resistors are available in much finer variations and at higher tolerances than ordinary capacitors, so you usually find a close capacitor value, then let that drive the exact resistor value.
So we've settled on R = 10 kΩ and C = 2 nF. Note that this has come from the 8 kHz upper frequency requirement. We have no more choices to make, so the settling time and signal to noise ratio will be what it will be. All we can do now is determine whether it will be good enough, or conversely, what PWM characteristics would be necessary to support the output signal specs.
Since the spec was a signal to noise ratio of 60 dB, that means the noise must be less than 1 part in 1000 of the voltage, which means the PWM frequency must be attenuated by that much. A single R,C filter attenuates inversely proportional to frequency after the rolloff frequency. This is a approximation that breaks near the rolloff frequency and below, but it's good enough in most cases after a octave or two past the rollof frequency. In other words, 16 kHz will be attenuated by 2 with some error, 32 kHz by 4 with less error, and after that you can pretty much just divide the frequency of interest by the rolloff frequency to get attenuation. We want the PWM frequency to be attenuated by 1000, which means it needs to be 8 MHz or higher. That's high but doable with some processors. For example, some of the PIC 24H and dsPIC line have a special 'power supply control' PWM module that operate at just under 1 GHz.
Now let's look at the PWM resolution. Again, this is driven by the 60 dB signal to noise spec, which we know already means 1:1000. That would require a PWM resolution of at least 999 (you always get one more output level than the PWM resolution). That means the internal PWM slice clock needs to run 999 times the 8 MHz PWM output frequency, or basically 8 GHz. Not gonna happen with reasonably available off the shelf parts.
However, there is a way to get around these limitations, and that is to use more than just a single R,C filter. When I want a nice analog signal, I usually use two or three of them in succession. Let's see how using three successive R,C filters changes things.
We originally said our upper frequency of interest was 8 kHz, which implies we can tolerate that being 3 dB down unless we say otherwise. A single R,C filter will attenuate by 3 dB at the rolloff frequency, so we put it at right at 8 kHz. We can't have three filters at 8 kHz since they would attenuate by 9 dB there combined. So, we move the filters out by the number of poles (separate R,C filters in this case).
The three R,C filters (three poles) are therefore at 24 kHz. It seems like we lost ground doing this, but the big advantage is that the frequencies above that are now attenuated by the ratio cubed instead of just the ratio as with a single pole. Again we want the PWM frequency to be attenuated by 1000, which is 10^3, so we only need to be 10x beyond the filter rolloff frequencies which means 240 kHz is high enough. That's a big difference from 8 MHz. Now the internal PWM clock or PWM slice frequency only needs to be 240 MHz. That's still high but attainable.
Hopefully this has given you some insight into the issues. If you provide concrete specs we can work thru specific values for your case.
Olin LathropOlin Lathrop
It's possible to improve performance over a single RC by using cascaded RC stages. One cannot get as good performance in a pure multi-stage RC passive filter as can be obtained from active filters, but performance may nonetheless be better than with a single stage. Unfortunately, I don't know any particular good methods for computing optimal RC values.
Another thing to note is that while pulse-width modulation is the most common form of duty-cycle modulation, it is not the only one. One simple approach which can be very useful in cases where the target output voltage won't be changing too often, and where the output is more likely to be near the center of the range than at the edges, is to generate a set of signals by computing (current counter value 'and not' previous counter value), and ANDing that signal with the bits of desired data value, in reverse order (so that the MSB of the data value gets AND'ed with the xor of the present counter LSB and the previous one). Using such an approach with e.g. six-bit duty cycle modulation would mean a 32/64 duty cycle wave will be represented by a frequency of half the PWM clock, rather than square wave with a frequency 1/64 of the PWM clock. A 33/64 duty cycle would be represented mostly by a frequency of half the PWM clock, but with some extra high pulses thrown in.
Here's a demo of what I'm talking about.
supercatsupercatAll great answers given so far, well written and relevant, but often the best answer needs a better question.
When you consider 'best amount of RC?', what assumptions need to be considered for any design;
What is impedance of filter relative to impedance of source and load?
If not critical, choose R in between source and load. But say if CMOS driver is a value 10~100 Ω and say load is 100KΩ, but you want 0.3% accuracy on DC loss, then choose R << 0.3% of R-load, or as I call it 'impedance ratio method' for loading considerations so here R < 0.003 * 1e5 = 300Ω. This choice of R is not critical, but you must take care not to load filter, so you may choose by impedance ratios for quick calculation on DC loss and AC rejection.
- if you wanted noise @ 10KHz PWM to be <1% of source, then choose impedance of Zc(f) to be <1% of R for series RC LPF.
- if you wanted ripple >80dB down on all harmonics above 0.5 MHz for interference reasons, say on AM radio or FCC/CE EMC tests, again look at impedance ratio of cap including ESR relative to R estimate a value of C then choose slightly bigger with margin for temp. tolerance and consider how much margin you need. You know that 1st order filters have a slope of 20dB/decade and then you can decide if 1st order filter is sufficient. Cascading RC filters must consider the loading effects on each stage. LC filters cost more and active filter may be needed.
Assuming you know impedance of a capacitor impedance ratio criteria is a simple solution. Otherwise to find an impedance in the middle of source and load consider one method Rf = √(Rs*Rl), where Rf is filter RC value for source, Rs and load Rl as one method for middle range.
The nice thing about design, is depending on your criteria, there are often multiple 'best' answers for RC value. :)
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Sunnyskyguy EE75Sunnyskyguy EE75Determine the best RC time constant in PWM digital to analog low-pass filter?
The best answer depends on a different questions;
? What is the spectrum of the original data? BW=? ? How much rejection of PWM carrier is acceptable? Atten= 40dB? 60? 10??
To design a filter based on time constant alone neglects the more importance of understanding the preservation of data. It is best to define the original signal so one can design a simple 'optimal matched filter' We need to care about preservation of the original signal and rejection of the carrier signal (PWM f).
You can choose any Nth order LPF to match the filter to the original signal.Simple 1 chip switched capacitor filters or active filters will give the best results. THe type of LPF depends on the criteria of matching the original signal.
Pick Best = maximally flat freq. response, or m.f. group delay or steepest skirts or a Nyquist filter to 1/2 PWM f.
Then next best method:
Warcraft 3 battlenet download mac. define the amount of jitter in the voltage from imperfect RC filters.
If one was designing a PLL VCXO for RF and used PWM to control the loop, you might care about spurious sidebands from the PWM, so you need to consider a LPF with a notch at PWM THis is easy once you get the answer for;
How much rejection of PWM carrier is acceptable
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Create an FIR Filter Using Integer Coefficients
Digital Filter Design Tutorial
This section provides an example of how you can create a filterwith integer coefficients. In this example, a raised-cosine filterwith floating-point coefficients is created, and the filter coefficientsare then converted to integers.
Define the Filter Coefficients
To illustrate the concepts of using integers with fixed-pointfilters, this example will use a raised-cosine filter:
Thecoefficients ofb are normalized so that the passbandgain is equal to 1, and are all smaller than 1. In order to make themintegers, they will need to be scaled. If you wanted to scale themto use 18 bits for each coefficient, the range of possible valuesfor the coefficients becomes:Because the largestcoefficient of b is positive, it will need to bescaled as close as possible to 131071 (without overflowing) in orderto minimize quantization error. You can determine the exponent ofthe scale factor by executing:
Alternatively, you can use the fixed-point numbers autoscalingtool as follows:
It is a coincidence that B and L areboth 18 in this case, because of the value of the largest coefficientof b. If, for example, the maximum value of b were0.124, L would be 20 while B (thenumber of bits) would remain 18.
Build the FIR Filter
First create the filter using the direct form, tapped delayline structure:
In order to set the required parameters, the arithmetic mustbe set to fixed-point:
You can check that the coefficients of h areall integers:
Now you can examine the magnitude response of the filter using fvtool:
This shows a large gain of 117 dB in the passband, which isdue to the large values of the coefficients— this will causethe output of the filter to be much larger than the input. A methodof addressing this will be discussed in the following sections.
Set the Filter Parameters to Work with Integers
You will need to set the input parameters of your filter toappropriate values for working with integers. For example, if theinput to the filter is from a A/D converter with 12 bit resolution,you should set the input as follows:
The info method returns a summary of thefilter settings.
In this case, all the fractional lengths are now set to zero,meaning that the filter h is set up to handle integers.
Create a Test Signal for the Filter
You can generate an input signal for the filter by quantizingto 12 bits using the autoscaling feature, or you can follow the sameprocedure that was used for the coefficients, discussed previously.In this example, create a signal with two sinusoids:
Filter the Test Signal
To filter the input signal generated above, enter the following:
Here ysc is a full precision output, meaningthat no bits have been discarded in the computation. This makes ysc thebest possible output you can achieve given the 12–bit inputand the 18–bit coefficients. This can be verified by filteringusing double-precision floating-point and comparing the results ofthe two filtering operations:
Now you can examine the output compared to the input. This exampleis plotting only the last few samples to minimize the effect of transients:
It is difficult to compare the two signals in this figure becauseof the large difference in scales. This is due to the large gain ofthe filter, so you will need to compensate for the filter gain:
You can see how the signals compare much more easily once thescaling has been done, as seen in the above figure.
Truncate the Output WordLength
If you examine the output wordlength,
you will notice that the number of bits in the output is considerablygreater than in the input. Because such growth in the number of bitsrepresenting the data may not be desirable, you may need to truncatethe wordlength of the output. The best way to do this is to discardthe least significant bits, in order to minimize error. However, ifyou know there are unused high order bits, youshould discard those bits as well.
To determine if there are unused most significant bits (MSBs),you can look at where the growth in WordLength arises in the computation.In this case, the bit growth occurs to accommodate the results ofadding products of the input (12 bits) and the coefficients (18 bits).Each of these products is 29 bits long (you can verify this using info(h)).The bit growth due to the accumulation of the product depends on thefilter length and the coefficient values- however, this is a worst-casedetermination in the sense that no assumption on the input signalis made besides, and as a result there may be unused MSBs. You willhave to be careful though, as MSBs that are deemed unused incorrectlywill cause overflows.
Digital Filter Design Using Matlab
Suppose you want to keep 16 bits for the output. In this case,there is no bit-growth due to the additions, so the output bit settingwill be 16 for the wordlength and –14 for the fraction length.
Since the filtering has already been done, you can discard somebits from ysc:
Alternatively, you can set the filter output bit lengths directly(this is useful if you plan on filtering many signals):
You can verify that the results are the same either way:
However, if you compare this to the full precision output, youwill notice that there is rounding error due to the discarded bits:
In this case the differences are hard to spot when plottingthe data, as seen below:
Scale the Output
Because the filter in this example has such a large gain, theoutput is at a different scale than the input. This scaling is purelytheoretical however, and you can scale the data however you like.In this case, you have 16 bits for the output, but you can attachwhatever scaling you choose. It would be natural to reinterpret theoutput to have a weight of 2^0 (or L = 0) for the LSB. This is equivalentto scaling the output signal down by a factor of 2^(-14). However,there is no computation or rounding error involved. You can do thisby executing the following:
This plot shows that the output is still larger than the input.If you had done the filtering in double-precision floating-point,this would not be the case— because here more bits are beingused for the output than for the input, so the MSBs are weighted differently.You can see this another way by looking at the magnitude responseof the scaled filter:
This plot shows that the passband gain is still above 0 dB.
To put the input and output on the same scale, the MSBs mustbe weighted equally. The input MSB has a weight of 2^11, whereas thescaled output MSB has a weight of 2^(29–14) = 2^15. You needto give the output MSB a weight of 2^11 as follows:
This operation is equivalent to scaling the filter gain downby 2^(-18).
The above plot shows a 0 dB gain in the passband, as desired.
With this final version of the output, yf isno longer an integer. However this is only due to the interpretation-the integers represented by the bits in yf areidentical to the ones represented by the bits in yri.You can verify this by comparing them:
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Configure Filter Parameters to Work with Integers Using the set2int Method
Set the Filter Parameters to Work withIntegers
The set2int method provides a convenientway of setting filter parameters to work with integers. The methodworks by scaling the coefficients to integer numbers, and settingthe coefficients and input fraction length to zero. This makes itpossible for you to use floating-point coefficients directly.
The coefficients are represented with 18 bits and the inputsignal is represented with 12 bits:
The set2int method returns the gain of thefilter by scaling the coefficients to integers, so the gain is alwaysa power of 2. You can verify that the gain we get here is consistentwith the gain of the filter previously. Now you can also check thatthe filter h is set up properly to work with integers:
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Here you can see that all fractional lengths are now set tozero, so this filter is set up properly for working with integers.
Reinterpret the Output
You can compare the output to the double-precision floating-pointreference output, and verify that the computation done by the filter h isdone in full precision.
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You can then truncate the output to only 16 bits:
Once again, the plot shows that the input and output are atdifferent scales. In order to scale the output so that the signalscan be compared more easily in a plot, you will need to weigh theMSBs appropriately. You can compute the new fraction length usingthe gain of the filter when the coefficients were integer numbers:
This final plot shows the filtered data re-scaled to match theinput scale.